Many high-speed electronic systems utilize both the rising and falling edges of a clock signal to double the speed of the system without doubling the clock rate. In such systems, the proper duty cycle of the clock signal is critical, for example to latch data at the appropriate time. The duty cycle may be distorted, however, due to variations in signal propagation paths and other factors. Thus, an intended 50% duty cycle may become skewed in operation, which may disrupt the proper operation of the system.
Many systems include a duty cycle correction circuit to maintain the desired duty cycle. Referring to FIG. 8, a conventional duty cycle corrector comprises three stages. Typically, a duty cycle detector 710 uses a capacitor to convert the duty cycle information into an analog signal having a magnitude proportional to the duty cycle difference. The difference is amplified or compared to a constant reference voltage by an amplifier or comparator 712 to generate an adjustment signal to adjust the duty cycle. The adjustment signal is used by an adjustment circuit 714 to adjust the duty cycle of the signal so that the desired duty cycle is attained. Such systems, however, require maintenance of the reference voltage at a constant level, which may be difficult or impossible to maintain. Further, such circuits require time to settle to the proper duty cycle, and may be sensitive to noise as well.